1. Field of the Invention
The present invention relates to a driving circuit for driving source lines of an active-matrix type liquid crystal display having a thin film transistor matrix array (TFT array).
2. Description of the Prior Art
Conventionally, there has been proposed a circuit for driving source lines of an active-matrix type liquid crystal display as shown in FIG. 6.
In FIG. 6, the reference numeral 21 denotes a timing generating circuit. The timing generating circuit 21 receives horizontal and vertical synchronizing signals HD and VD as reference timing signals. The horizontal and vertical synchronizing signals HD and VD are synchronized with analog video signals to be described below.
A shift register circuit 22 receives sampling clocks CK and start pulses P ST from the timing generating circuit 21.
Analog video signals SVa are supplied to a sampling gate circuit 23. The gate circuit 23 has a plurality of gate portions. The gate portions sample the video signals Sva to obtain pixel signals. In addition, the gate portions receive gate pulses P SG from the shift register circuit 22 to sample the pixel signals for one line for each horizontal period.
A latch gate circuit 24 receives the pixel signals for one line which are sampled by the gate circuit 23. Latch pulses P LG are supplied from the timing generating circuit 21 to the gate circuit 24 for a horizontal blanking period. Consequently, the pixel signals for one line supplied from the gate circuit 23 are latched and held for a next horizontal period.
The pixel signals for one line outputted from the gate circuit 24 are simultaneously supplied to corresponding source lines ls of a TFT array 10 through an output circuit 25.
FIG. 7 is a diagram showing a specific partial construction of the gate circuits 23 and 24 and the output circuit 25 corresponding to one pixel signal. In other words, the whole of the gate circuits 23 and 24 and the output circuit 25 consists of the predetermined number of the above constructions. The reference numerals G23 and G24 denote gates. The reference numerals C23 and C24 denote capacitors. The reference numeral A25 denotes a buffer.
Returning to FIG. 6, the timing generating circuit 21 supplies control signals to a gate driving circuit 26. Then, scanning pulses are sequentially supplied to gate lines lg. The gate lines lg are arranged in positions corresponding to the pixel signals for one line which are supplied to the source lines ls of the TFT array 10 through the output circuit 25.
According to the driving circuit shown in FIG. 6, the analog video signals SVa are inputted. Therefore, if the number of pixels for one line is increased like the TFT array 10 having a large screen and high quality of image, a sampling time which is allowed for one pixel signal becomes shorter. Consequently, the time for charging the capacitor C23 of the gate circuit 23 becomes insufficient so that the video signals SVa cannot be sampled accurately. In other words, the TFT array 10 cannot accurately be driven corresponding to the video signals SVa. Therefore, it is difficult to obtain the good quality of display.
Japanese Unexamined Patent Publication Nos. 63-182695 and 63-186295 have disclosed a circuit for driving the liquid crystal display in response to digital video signals. In the former Publication disclosed is a driving circuit for selecting driving voltages corresponding to inputted multigradation digital video signals to output the same to the liquid crystal display. In the latter Publication disclosed is a driving circuit for receiving data which specifies a display brightness for each pixel of the liquid crystal display on the basis of a value represented by a plurality of bits and then outputting a driving signal having a pulse width corresponding to the data.